| 摘要 |
PROBLEM TO BE SOLVED: To prevent the occurrence of a punch-through current in an output transistor by shortening the clock access time during a period from the input of an external clock signal to the output of data by providing a voltage converting circuit on a data bus in the preceding stage of a latch circuit which decides the outputting timing of the data. SOLUTION: Although the operations of a signalsϕ4 at a point on an input circuit side becomes a little slower while the signalϕ4 is generated from a NAND circuit NAN 1, because a voltage converting circuit 56 is provided. However, since the capacity of the wiring which transmits the signalϕ4 is made larger than the conventional example, the operation of a latch circuit 119 becomes slower. Therefore, the clock access time during a period from the input of the signalϕ4 to the output of data is shortened by transmitting a voltage-converted signal having a large amplitude and providing the circuit 56 in the preceding stage of the latch circuit 119. In the routes of data signals which are outputted from the latch circuit 119 and transmitted to output transistors TR1 and TR2, no voltage delay occurs and both the output transistors TR1 and TR2 are turned on and prevent the flowing of a punch through current.
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