| 摘要 |
An EEPROM operable at a reduced power source voltage comprises a decoder circuit for decoding input signals, a memory array for storing the decoded, a reading circuit for operating the decoder circuit and the memory array, and for reading out data stored in the memory array, and a writing circuit for operating the decoder circuit and the memory array, and for writing data to the memory array. The EEPROM is divided into a first circuit area comprising a plurality of first transistors driven by a first power source voltage, an absolute value of a threshold voltage of the first transistors in the first circuit area being within the range of approximately 0.3 V to 0.7 V, the first circuit area including at least the reading circuit, and a second circuit area comprising a plurality of second transistors driven by a second power source voltage, an absolute value of a threshold voltage of the second transistors in the second circuit area being within the range of approximately 0.7 V to 0.9 V, the second circuit area including at least the writing circuit.
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