| 发明名称 |
METHOD AND APPARATUS FOR INTEGRATED CIRCUIT LAYOUT |
| 摘要 |
A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process. |
| 申请公布号 |
US2016370698(A1) |
申请公布日期 |
2016.12.22 |
| 申请号 |
US201615188753 |
申请日期 |
2016.06.21 |
| 申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD. |
发明人 |
Chen Yi-Fan;Hsieh Tung-Heng;Hou Chin-Shan;Wu Yu-Bey |
| 分类号 |
G03F1/36;G06F17/50 |
主分类号 |
G03F1/36 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A method comprising:
receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary; placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable; and performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process. |
| 地址 |
Hsin-Chu TW |
