发明名称 Semiconductor device and manufacturing method thereof
摘要 Of three chips (2A), (2B), and (2C) mounted on a main surface of a package substrate (1) in a multi-chip module (MCM), a chip (2A) with a DRAM formed thereon and a chip (2B) with a flash memory formed thereon are electrically connected to wiring lines (5) of the package substrate (1) through Au bumps (4), and a gap formed between main surfaces (lower surfaces) of the chips (2A), (2B) and a main surface of the package substrate (1) is filled with an under-fill resin (6). A chip (2C) with a high-speed microprocessor formed thereon is mounted over the two chips (2A) and (2B) and is electrically connected to bonding pads (9) of the package substrate (1) through Au wires (8).
申请公布号 US9613922(B2) 申请公布日期 2017.04.04
申请号 US201414582733 申请日期 2014.12.24
申请人 Renesas Electronics Corporation 发明人 Kado Yoshiyuki;Naito Takahiro;Sato Toshihiko;Ikegami Hikaru;Kikuchi Takafumi
分类号 H01L23/04;H01L25/18;H01L23/00;H01L23/31;H01L23/50;H01L23/538;H01L25/065;H01L23/28 主分类号 H01L23/04
代理机构 Shapiro, Gabor and Rosenberger, PLLC 代理人 Shapiro, Gabor and Rosenberger, PLLC
主权项 1. A semiconductor device, comprising: a package substrate including: a substrate having, in a cross section view, a surface extended in a first direction and a cutting surface extended in a second direction, the second direction crossing the first direction;wirings formed on the surface of the substrate; anda solder resist formed over the surface of the substrate such that each of the wirings is overlapped with the solder resist and such that each of parts of the wirings is exposed from the solder resist; first portions where the solder resist is not present; a second portion where the solder resist is not present, the second portion being a different portion than the first portions; a semiconductor chip mounted on the package substrate; plating layers formed on the parts of the wirings, respectively; bumps disposed on the parts of the wirings via the plating layers, respectively; and a sealing resin sealing the semiconductor chip, wherein, in plan view, the parts of the wirings which are exposed from the solder resist at the first portions, are arranged along each side of the surface of the substrate, wherein no part of each of the wirings is present at the second portion, wherein, in plan view, the second portion surrounds the parts of the wirings, wherein, in the cross section view, the solder resist has a side surface located at the second portion, the side surface of the solder resist being located more inwardly from a side of the substrate in the first direction than the cutting surface of the substrate, and wherein an end surface of each of the wirings, which is directed toward the second portion, is exposed from the solder resist.
地址 Tokyo JP