Sampling circuit

摘要

A sampling circuit includes a first latch, a second latch and a signal transition detector. The first latch is disposed on an upstream side of a logic circuit. The second latch is disposed on a downstream side of the logic circuit. The first latch and the second latch respectively switch to opposite states of an opaque state or a transparent state according to trigger signals generated by a reference clock and a control clock. The signal transition detector is configured for detecting whether the signal outputted by the logic circuit is in error or not and outputting a corresponding control clock. The above-mentioned sampling circuit can delay switching the second latch to the opaque state and switching the first latch to the transparent state to correct sampling when a timing error occurs.

主权项

1. A sampling circuit comprising:
a first latch disposed on an upstream side of a logic circuit, receiving a first input signal, outputting a first output signal to said logic circuit, and switching to an opaque state or a transparent state according to a first trigger signal generated by a reference clock and a control clock; a second latch disposed on a downstream side of said logic circuit, receiving a second input signal from said logic circuit, outputting a second output signal, and switching to an opaque state or a transparent state according to a second trigger signal generated by said reference clock and said control clock, wherein a state of said first latch is opposite to a state of said second latch; and a signal transition detector electrically connected with said logic circuit, and detecting whether said second input signal outputted by said logic circuit is incorrect, and outputting a corresponding said control clock.