| 摘要 |
An input buffer protection circuit is disclosed which comprises a NMOS transistor with a source, drain and gate coupled to an input terminal of the input buffer, a pad and a chip peripheral positive power supply voltage (VDDP), respectively, and a PMOS transistor with a source, drain and gate coupled to the pad, the input terminal of the input buffer and a first terminal of a biasing circuit, respectively, wherein the biasing circuit has a second terminal coupled to the pad and generates at the first terminal a voltage lower than the pad's input signal voltage (VPAD) to turn on the PMOS transistor when the VPAD is lower than or equal to the VDDP, or a voltage substantial equals to the VPAD to turn off the PMOS transistor when the VPAD is higher than the VDDP.
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