发明名称 |
Semiconductor device with low on resistance and method for fabricating the same |
摘要 |
A semiconductor device and a fabricating method thereof are provided. The semiconductor device include: a trench disposed within a substrate, the trench comprising an upper trench part that is wider than a lower trench part in width; a gate disposed in the trench; an interlayer insulating layer pattern disposed above the gate in the trench; a source region disposed within the substrate and contacting a sidewall of the upper trench part; a body region disposed below the source region in the substrate; and a contact trench disposed above the body region and filled with a conductive material. |
申请公布号 |
US9099554(B2) |
申请公布日期 |
2015.08.04 |
申请号 |
US201314080465 |
申请日期 |
2013.11.14 |
申请人 |
MagnaChip Semiconductor, Ltd. |
发明人 |
Kang SooChang;Kim YoungJae |
分类号 |
H01L21/00;H01L29/78;H01L21/762;H01L29/66;H01L29/423 |
主分类号 |
H01L21/00 |
代理机构 |
NSIP Law |
代理人 |
NSIP Law |
主权项 |
1. A method for fabricating a semiconductor device comprising:
forming a pad oxide layer pattern and a pad nitride layer pattern on a substrate; selectively etching the substrate using the pad nitride layer pattern as an etching mask, to form an upper trench part within the substrate; forming a nitride layer on the pad nitride layer pattern and the pad oxide layer pattern including the surface of the upper trench part; etching an entire surface of the nitride layer to form a nitride layer pattern on a sidewall of the upper trench part and sidewalls of the pad nitride layer pattern and the pad oxide layer pattern; etching the substrate beneath the upper trench part using the pad nitride layer pattern and the nitride layer pattern as an etching mask, to form a lower trench part; etching the nitride layer pattern, the pad nitride layer pattern and the pad oxide layer pattern located on the sidewall of the upper trench part, to form a trench having the lower trench part and the upper trench part, the upper trench part being wider than the lower trench part in width; forming a gate insulating layer on a surface of the trench; depositing polysilicon on the gate insulating layer within the lower trench part and the upper trench part; forming a body region within the epitaxial layer of the substrate; etching the polysilicon to form a gate within the lower trench part; forming a source region on a side surface of the upper trench part; forming an interlayer insulating layer pattern on the gate insulating layer within the upper trench part; forming a contact trench to allow the source region and the body region to contact each other; forming an impurity region beneath the contact trench, the impurity region having the same type of impurity as the body region and having a higher concentration of impurity than the body region; and filling the contact trench with a metal layer. |
地址 |
Cheongju-si KR |