Memory having power saving mode

摘要

A memory especially suitable for SRAM arrays has a normal mode and a power saving mode (figure 3). The memory has bitline precharge circuitry 20, P7-P9 which during the normal mode (PD=0, PS=0) selectively couples a pair of bitlines 12, 13 to a precharge node to charge the bitlines to a given voltage level. During the power saving mode (PD=0, PS=1 PRC=1) the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level VDD during the normal mode and at a second voltage VVDP level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode. The circuit may comprise a voltage control circuit in the form of a voltage limiting circuit comprising a diode connected transistor, for example a gate-drain shorted PMOSFET device P2 coupled between the first node and the precharge node. During the power save mode, the storage circuit (for example SRAM cell) may remain powered on. A method of operation is also included.