| 发明名称 |
DYNAMIC PARTIAL POWER DOWN OF MEMORY-SIDE CACHE IN A 2-LEVEL MEMORY HIERARCHY |
| 摘要 |
A system and method are described for flushing a specified region of a memory side cache (MSC) within a multi-level memory hierarchy. For example, a computer system according to one embodiment comprises: a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC. |
| 申请公布号 |
US2014304475(A1) |
申请公布日期 |
2014.10.09 |
| 申请号 |
US201113994726 |
申请日期 |
2011.12.20 |
| 申请人 |
Ramanujan Raj K;Hinton Glenn J;Zimmerman David J |
发明人 |
Ramanujan Raj K;Hinton Glenn J;Zimmerman David J |
| 分类号 |
G06F12/08 |
主分类号 |
G06F12/08 |
| 代理机构 |
|
代理人 |
|
| 主权项 |
1. A computer system comprising:
a memory subsystem comprised of a non-volatile system memory and a volatile memory side cache (MSC) for caching portions of the non-volatile system memory; and a flush engine for flushing a specified region of the MSC to the non-volatile system memory in response to a deactivation condition associated with the specified region of the MSC. |
| 地址 |
Federal Way WA US |
