SINGLE-EVENT LATCH-UP PREVENTION TECHNIQUE FOR SEMICONDUCTOR DEVICE

摘要

PROBLEM TO BE SOLVED: To provide a technique for addressing single-event latch-up (SEL) in a semiconductor device.SOLUTION: A technique for addressing single-event latch-up (SEL) in a semiconductor device includes determining a location of a parasitic silicon-controlled rectifier (SCR) 600 in an integrated circuit design of the semiconductor device. In this case, the parasitic SCR 600 includes a parasitic pnp bipolar junction transistor (BJT) and a parasitic npn BJT. The technique also includes incorporating a first transistor between a first power-supply node VDD and an emitter of the parasitic pnp BJT in the integrated circuit design. The first transistor 502 includes a first terminal coupled to the first power-supply node VDD, a second terminal coupled to the emitter of the parasitic pnp BJT, and a control terminal. The first transistor 502 is not positioned between a base of the pnp BJT and the first power-supply node VDD. The first transistor 502 limits current conducted by the parasitic pnp bipolar junction transistor following an SEL.