发明名称 |
INITIALIZATION OF MULTI-CORE PROCESSING SYSTEM |
摘要 |
This disclosure is directed to use of shared initialization and configuration vectors, which are delivered to processing cores in a multi-core processor using packets. An initialization core may include reset logic that may read initialization and configuration vectors from a centralized storage location, which may be on a die containing the processing cores (e.g., a fuse, etc.), off the die (e.g., in volatile memory, flash memory, etc.), or a combination of both. The initialization core may then generate packets to transmit the initialization and configuration vectors to processing cores that await initialization (e.g., following a reset). In some instances, the initialization and configuration vector information may be shared by two or more cores of a same type. |
申请公布号 |
WO2013101093(A1) |
申请公布日期 |
2013.07.04 |
申请号 |
WO2011US67900 |
申请日期 |
2011.12.29 |
申请人 |
INTEL CORPORATION;CHANG, STEVEN, S.;THAKUR, ANSHUMAN;SUNDARARAMAN, RAMACHARAN CHARAN;MATAS, RAMON |
发明人 |
CHANG, STEVEN, S.;THAKUR, ANSHUMAN;SUNDARARAMAN, RAMACHARAN CHARAN;MATAS, RAMON |
分类号 |
G06F15/80;G06F13/14 |
主分类号 |
G06F15/80 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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