发明名称 MEMORY CONTROL DEVICE, AND MEMORY CONTROL METHOD
摘要 <p>Provided is a memory control device that enables the generic support of combinations of different data arrays at input and output when controlling multi-bank memory. The memory control device has: a write address generation means which outputs, on the basis of generic address generator (GAG) control information, a write address corresponding to each of a 1st to an Mth memory; a read address generation means which outputs, on the basis of the GAG control information, a read address corresponding to each of the 1st to the Mth memory; an input data selection control means which outputs, on the basis of the GAG control information, control information for an input data selection means and which exclusively assigns sets of input data which write to each of the 1st to the Mth memory; an output data selection control means which outputs, on the basis of the GAG control information, control information for an output data selection means and which exclusively assigns each set of data from the plurality of sets of data read from the 1st to the Mth memory; the input data selection means which exclusively selects and outputs, on the basis of the control information for the input data selection means, each set of data from the sets of the input data of an input data array; and the output data selection means which receives the plurality of sets of data simultaneously read out from each of the 1st to the Mth memory corresponding to the read address and, on the basis of the control information for the output data selection means, exclusively selects each set of data from the plurality of sets of data received, and outputs the output data of an output data array.</p>
申请公布号 WO2012070683(A1) 申请公布日期 2012.05.31
申请号 WO2011JP77441 申请日期 2011.11.22
申请人 NEC CORPORATION;ISHIHARA, NOZOMI;SEKI, KATSUTOSHI 发明人 ISHIHARA, NOZOMI;SEKI, KATSUTOSHI
分类号 G06F12/02;G06F12/06 主分类号 G06F12/02
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