| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a digital PLL which can simplify a circuit configuration and achieve area saving while satisfying property requirements. <P>SOLUTION: A digital PLL comprises: a TDC 101 which detects a phase difference between a reference clock signal FR and a frequency-divided clock signal FD; an FF 103 which outputs retard/advance of the FD and the FR; a phase difference computing unit 102; a digital filter 104 which smoothes a phase difference (PERR); a DCO 105 which outputs an output clock signal FO; an N divider 106 which outputs the FD which is obtained by dividing the FO; and a resistor 107 which samples a counter value within the N divider 106 in response to the FR. A phase difference detection measuring range of the TDC 101 is within one cycle of the FO, and the TDC 101 outputs a phase difference between the FR and the FD in a decimal converted to one cycle of the FO. The phase difference computing unit 102 calculates and outputs a PERR on the basis of an output of the resistor 107 and a code information sign if the phase difference between the FD and the FR is equal to or larger than an integral multiple of cycle of the FO, and on the basis of an output of the TDC and the code information sign if the phase difference between the FD and the FR is within one cycle of the FO. <P>COPYRIGHT: (C)2012,JPO&INPIT |
