发明名称 Power Consumption Reduction In A Multiprocessor System
摘要 Methods and apparatus provide for reducing power consumption by decreasing operating frequencies of waiting processors in a multiprocessor system. Power consumption may be reduced by having a processor enter a low frequency mode when the processor is in a loop waiting for data that have been locked by another processor. The frequency of operation of the waiting processor may be reduced to a fraction (one half, one quarter, etc.) of the normal, initial clock frequency. The multiprocessor system may monitor a number of times (loop count) that a waiting processor takes the wait loop and compare the number to a threshold. When the loop count is greater than or equal to the threshold, the clock frequency of the waiting processor is reduced. When the waiting processor ceases to wait and does not take the wait loop branch (e.g., because the other processor has released the lock on the data), the loop count is reset to zero and the frequency of operation of waiting processor is increased to an increased frequency, such as the normal, initial level.
申请公布号 US2011087909(A1) 申请公布日期 2011.04.14
申请号 US20100974124 申请日期 2010.12.21
申请人 SONY COMPUTER ENTERTAINMENT INC. 发明人 KANAKOGI TOMOCHIKA
分类号 G06F1/32 主分类号 G06F1/32
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