发明名称 |
Synergy Effect of Alloying Materials in Interconnect Structures |
摘要 |
A method of forming an integrated circuit structure, the method includes providing a semiconductor substrate; forming a dielectric layer over the semiconductor substrate; forming an opening in the dielectric layer; forming a seed layer in the opening; forming a copper line on the seed layer, wherein at least one of the seed layer and the copper line includes an alloying material; and forming an etch stop layer on the copper line.
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申请公布号 |
US2010059893(A1) |
申请公布日期 |
2010.03.11 |
申请号 |
US20090619484 |
申请日期 |
2009.11.16 |
申请人 |
CHANG HUI-LIN;LU YUNG-CHENG;JANG SYUN-MING |
发明人 |
CHANG HUI-LIN;LU YUNG-CHENG;JANG SYUN-MING |
分类号 |
H01L23/532 |
主分类号 |
H01L23/532 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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