发明名称 Apparatus and method for reducing drain modulation of high power transistor
摘要 An apparatus and a method for reducing drain modulation in a high power amplifier are provided, in which an adder supplies a current corresponding to a voltage reduced by a drain modulation, and a bias unit adds the current supplied from the adder to a DC bias and supplies the added current to a drain of a transistor. Accordingly, the drain modulation occurring in the transistor can be minimized and an output characteristic of the high power transistor can be improved.
申请公布号 US7400201(B2) 申请公布日期 2008.07.15
申请号 US20060480510 申请日期 2006.07.05
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 KIM KYOUNG-TAE
分类号 H03F3/04 主分类号 H03F3/04
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