| 摘要 |
PROBLEM TO BE SOLVED: To make a further reduction in ESL of a chip-type solid-state electrolytic capacitor to be used in various electronic apparatuses. SOLUTION: The chip-type solid-state electrolytic capacitor comprises a pair of positive pole COM terminals 4 joined to positive pole electrode portions 2 on both sides of an element laminate 1a consisting of capacitor elements 1 alternately stacked in opposite directions, negative pole COM terminal 5 joined on the bottom face of a negative pole electrode portion 3, a positive pole terminal 6 consisting of a pair of terminal portions 6a joined on the bottom faces of the positive pole COM terminals 4 and a plate-like inductor portion 6b connecting the pair of terminal portions 6a, a pair of negative pole terminals 7 joined to both sides of the bottom face of the negative pole COM terminal 5, and insulating outer-packaging resin 8 covering all these terminals. Due to this structure, magnetic fluxes generated by a current flowing between the terminals cancel each other, remarkably reducing ESL. Furthermore, the pair of terminal portions 6a of the positive pole terminal 6 connected by the inductor portion 6b form anπtype filter, which further reduces ESL. COPYRIGHT: (C)2008,JPO&INPIT
|
