发明名称 FAILURE ANALYZING SYSTEM, FAILURE ANALYZING METHOD AND EMULATOR DEVICE
摘要 A system and a method for analyzing failures, and an emulator thereof are provided to register break points in a program irrespective of the number of break point registers provided from a target device, such as a CPU, and obtain a plurality of events while the events are traced in the program operated in a ROM of the target device. An event tracer traces the event of the program executed in a target device(300). The target device has a debugging function including an event tracing function, a memory storing the program, and a CPU executing the program. An ICE(In-Circuit Emulator)(200) is connected to the CPU of the target device through an interface, and includes a CPU debugging function and a CPU control function for controlling the CPU through the interface. A host computer(100) includes a debugger(110) having an emulation control function associable with the emulator. The CPU control function has a function for issuing and outputting a forcible CPU break signal to the CPU of the target device. The CPU has the function for forcibly breaking operation executed at the inside by the forcible CPU break signal.
申请公布号 KR20080012222(A) 申请公布日期 2008.02.11
申请号 KR20070077067 申请日期 2007.07.31
申请人 KABUSHIKI KAISHA HITACHI SEISAKUSHO(D/B/A HITACHI, LTD.) 发明人 NAGANO TAKEHIKO;NOJIRI TOORU;SHIGEOKA TOMOHIKO
分类号 G06F11/00;G06F9/455 主分类号 G06F11/00
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