| 摘要 |
A device, a system, and a method for realizing a multi-state cache coherence scheme are provided to realize a multi-state cache coherence scheme in a computing platform including more than one processor core connected to a level-1 cache memory and a level-2 cache memory. A memory unit(150) stores a plurality of memory lines. A cache controller logic(193) sets an ID to relate at least one memory line with a cache coherency state ID, and to relate the first cache coherency state with at least one memory line in connection to the first component of the system. The cache controller logic sets the ID to relate the second coherency state with at least one memory line in the connection to the second component different from the first component. The memory unit includes a shared cache memory(121,122) among the processor cores(111,112) of a processing unit(101). The first component includes a private cache of at least one processor core, and the second component is placed to the outside of the processing unit.
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