发明名称 |
FIFO ALS ÜBERGANG VON TAKTREGIONEN |
摘要 |
A method and arrangement of passing data from a source clock domain to a non-synchronous receive clock domain are provided. A first processing circuit, located in the source clock domain, links write-address information with the data, and a clock generator generates a transmit clock signal in the source clock domain synchronous with a source clock. The first processing circuit transmits the clock signal and the data with the linked write-address information to a second processing circuit in the receive clock domain. In the receive clock domain, the second processing circuit writes the data at an address designating a storage element corresponding to the linked write-address information. The second processing circuit clocks the data into the storage element synchronous with the accompanying transmit clock signal responsive to a write enable signal from the source clock domain, and reads the data out of the storage element synchronous with a receive domain clock. |
申请公布号 |
AT348455(T) |
申请公布日期 |
2007.01.15 |
申请号 |
AT20020772679T |
申请日期 |
2002.10.02 |
申请人 |
KONINKLIJKE PHILIPS ELECTRONICS N.V. |
发明人 |
PONTIUS, TIMOTHY, A.;PAYNE, ROBERT, L.;EVOY, DAVID, R. |
分类号 |
H04L7/00;G06F5/10;H04L7/02;(IPC1-7):H04L7/02;G06F1/04;G06F5/06 |
主分类号 |
H04L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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