发明名称 Level shifter circuit and semiconductor memory device using same
摘要 A level shifter circuit comprises a first output MIS transistor of a first conductivity, and a second output MIS transistor of a second conductivity type having a second threshold voltage. The former has a first threshold voltage, wherein the output voltage is positively fed back to a gate terminal and the power supply voltage is applied to a first terminal to generate a first voltage at a second terminal. In the latter, the first voltage is applied to a first terminal and a second voltage is applied to a gate terminal to control conduction to generate the output voltage at a second terminal. The first and second charge type MIS transistors and the discharge MIS transistor are connected between the first terminal and gate terminal of the second output MIS transistor to charge or discharge the potential of the gate terminal of the second output MIS transistor.
申请公布号 US2006186942(A1) 申请公布日期 2006.08.24
申请号 US20060330143 申请日期 2006.01.12
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 FUTATSUYAMA TAKUYA;TAKEUCHI KEN
分类号 H03L5/00 主分类号 H03L5/00
代理机构 代理人
主权项
地址