发明名称 |
Dynamic test program generator for VLIW simulation |
摘要 |
A method for functional verification of a design for a parallel processing device includes receiving a sequence of single instructions from a dynamic test program generator, and assembling a plurality of the instructions from the sequence into an instruction word, in accordance with predetermined rules applicable to the parallel processing device. The instruction word is input to a simulator of the parallel processing device so as to determine a response of the device to the instruction word.
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申请公布号 |
US7085964(B2) |
申请公布日期 |
2006.08.01 |
申请号 |
US20010789430 |
申请日期 |
2001.02.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
FOURNIER LAURENT;RUBIN SHAI |
分类号 |
G06F11/26;G01R31/3181;G01R31/3183;G06F17/50 |
主分类号 |
G06F11/26 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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