| 摘要 |
PROBLEM TO BE SOLVED: To solve problems in semiconductor LSI, such as reduction of crosstalk and electric power consumption, timing optimization and improvement of chip yield, which are critical for chip performance and cost reduction among various problems caused by wiring. SOLUTION: To optimize wiring intervals, the degree of balance between wiring is defined. An evaluation function, in which weight coefficients are provided for the product of wiring lengths that corresponds to original wiring intervals, is used and optimization is realized by minimizing or maximizing the value of the function. In addition, a function that expresses yield, which measures defect density depending on the value of wiring intervals, is also used to calculate wiring balance that improves yield. These technologies realize timing optimization and layout to reduce crosstalk for LSI chips, and also generate layout patterns to improve yield, so that they are very useful. COPYRIGHT: (C)2006,JPO&NCIPI
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