| 摘要 |
A delay compensation technique for two lines or more using multiple sample/hold stages clocked by a multi-phase clock is disclosed. Each line has a delay compensation circuit so as to adjusts the delay of the line to match others. Each phase of the clock samples the input data at certain time intervals, T, where the sampling time intervals are typically equal to a symbol period. By selecting and multiplexing the proper sample/hold data to output in each delay compensation circuit, the outcoming samples are aligned within a time interval. The select signal of each multiplexer selects only one sample/hold output and rotate at a frequency of 1/T. The sample/hold stages not selected at the time can be turned off to save power. The outputs from the multiplexers of the multiple lines can be further fine aligned by continuously moving the multiplexer select signal versus the sampling clocks. The delay compensation technique in accordance with the present invention can be combined with a finite impulse response (FIR) filter using rotating tap weights. Combining the filter and the delay stage together has the advantage of limiting the sample/hold stages the signal needs to go through to one. Also the ON sample/hold stage of the delay compensation circuit in the combined configuration is in fact the FIR stages with rotating tap weights. Therefore in the combination circuit, the delay matching comes at no extra power. |
