DATA LATCH CIRCUIT IMPROVED IN OPERATIONAL SPEED

摘要

PURPOSE: A data latch circuit improved in an operational speed is provided to reduce the time from the input point of the data to the output point of the data by reducing the time passing through the cascode logic circuit. CONSTITUTION: A data latch circuit(300) improved in an operational speed includes a sense amplifier(310), a clock latch circuit(320), a multiplexer(340) and a cascode logic circuit(350). The sense amplifier(310) outputs a first inverse signal and a second inverse signal. The clock latch circuit(320) generates the gated clock signal enabled in response to the enable signal and the clock signal when the enable signal and the clock signal are the first level at the same time. The multiplexer(340) outputs the first signal as the output data and the first inverse signal as the feedback data when the enable signal is the first level and outputs the second signal as the output data and the second inverse signal as the feedback signal when the enable signal is the second level. And, the cascode logic circuit(350) receives the output data and the feedback data and generates the cascode output data in response to the gated clock signal.