发明名称 GRID CLOCK DISTRIBUTION NETWORK TO MINIMIZE CLOCK SKEW
摘要 PURPOSE: A grid clock distribution network to minimize clock skew is provided which minimizes skew between clock signals arriving at each part of a chip area. CONSTITUTION: A number of clock drivers(220) are arranged around a chip area(210), and receive and output a clock signal. A grid distribution network(230) distributes the clock signal being output from the above clock drivers to the above chip area. The driving capability of the above clock drivers increases as the distance of a check point going to the center of each side of the chip area, and it decreases as the distance of the check point going to an end point of each side of the above chip area. The driving capability of the clock drivers is proportional to a distance from the end point of each side of the chip area.
申请公布号 KR20040011664(A) 申请公布日期 2004.02.11
申请号 KR20020044676 申请日期 2002.07.29
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 LEE, DONG HYEON
分类号 G06F1/10;H03K5/00;H04L7/00;(IPC1-7):G11C7/22 主分类号 G06F1/10
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