| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a technology to enhance the reliability of a semiconductor memory device. <P>SOLUTION: Mask patterns, including patterns 40 corresponding to openings, patterns 41 corresponding to grooves, and dummy patterns 50-55 not transferred onto photoresist, are formed on a photo mask 34. The patterns 40 are arranged like a matrix with a pitch P2 in a row direction and a pitch P1 in a column direction. The dummy patterns 50 make the pitch P2 with the patterns 40 arranged in the column direction, while the dummy patterns 51 make the pitch P1 with the patterns in the row direction. Using the photo mask 34, openings for bottom electrodes of a capacitor are formed in an insulating layer in a memory cell array formation region, and grooves are formed in the insulating layer in a boundary between the memory cell array formation region and a peripheral circuit formation region. <P>COPYRIGHT: (C)2004,JPO |
