Solid-state image sensing device

摘要

When a signal output by a solid-state image sensing device is clamped to a predetermined reference potential, a high voltage generated in a transfer suspension period after the clamping is generally supplied to an A/D converter as generated. A sample/hold output Va is clamped to a clamp level Vref over a period of time between a halfway point of time of a signal of a picture element preceding ahead by one line and the end of an inhibit period of transfer clocks âH1 and âH2 of a signal output by an empty transmission unit 13a by means of a clamp pulse âCLP1 and a sample/hold output Va for the second picture element or a subsequent one of an OPB unit 11a is clamped to a clamp level Vref by means of a clamp pulse âCLP2 so as to prevent a signal output Vout exceeding a reference voltage from being supplied to an A/D converter at a later stage.