发明名称 |
Nucleation for improved flash erase characteristics |
摘要 |
The present invention provides a method for improving the erase speed and the uniformity of erase characteristics in erasable programmable read-only memories. This result is achieved by forming polycrystalline floating gate layers with optimized grain size on a tunnel dielectric layer. Nucleation sites are formed by exposing the tunnel dielectric layer to a first set of conditions including a first temperature and a first atmosphere selected to optimize nucleation site size and distribution density across the tunnel dielectric layer. A polycrystalline floating gate layer is formed on top of the nucleation sites by exposing the nucleation sites to a second set of conditions including a second temperature and a second atmosphere selected to optimize polycrystalline grain size and distribution density across the polycrystalline floating gate layer.
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申请公布号 |
US6455372(B1) |
申请公布日期 |
2002.09.24 |
申请号 |
US20000639580 |
申请日期 |
2000.08.14 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
WEIMER RONALD A. |
分类号 |
H01L21/205;H01L21/28;H01L21/3205;H01L29/423;H01L29/49;(IPC1-7):H01L21/336;H01L21/20;H01L29/788 |
主分类号 |
H01L21/205 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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