发明名称 |
ZERO-DELAY BUFFER CIRCUIT FOR A SPREAD SPECTRUM CLOCK SYSTEM AND METHOD THEREFOR |
摘要 |
A clock recovery circuit and a method for reducing electromagnetic emission (EMI) and increasing an attainable clock frequency includes a spread spectrum clock (SSC) generator that receives an input clock signal and generates a frequency-modulated clock signal, and a zero-delay buffer circuit that receives and buffers said modulated clock frequency signed to generated an output clock signal. The frequency-modulated clock signal and the output clock signal are phase-aligned such that there is no phase difference between the output clock signal and the modulated frequency clock signal. The clock recovery circuit also includes a delay-locked loop (DLL) circuit that reduces related art jitter and skew characteristics, and a phase detector circuit that eliminates phase ambiguity problems of a related art phase detector. |
申请公布号 |
EP1238461(A1) |
申请公布日期 |
2002.09.11 |
申请号 |
EP20000978095 |
申请日期 |
2000.11.11 |
申请人 |
LEE, KYEONGHO |
发明人 |
LEE, KYEONGHO;PARK, JOONBAE |
分类号 |
H03L7/081;G06F1/04;G06F1/10;H03L7/07;H03L7/089;H03L7/23;H04B15/04;H04L7/033 |
主分类号 |
H03L7/081 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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