| 摘要 |
PURPOSE: A device for arbitrating duplexed common buses between the main and peripheral processors of a full electronic exchange, is provided to arbitrate the duplexing common buses to transmit data through two active common buses, when many peripheral processors operated as bus masters transmit data to the main processor through the duplexed common buses, so as to receive data through another common bus even when a line fault is generated in the specific receiver of a common bus. CONSTITUTION: Peripheral processors decide a main transmission port according to the control of a central processing unit(CPU) and make the decided transmission port active. And the peripheral processors make another transmission port active after a predetermined time, to arbitrate the duplexed common buses. A main processor normally receives a signal through another common bus, even when one common bus has a fault, by receiving signals transmitted from the peripheral processors respectively through the two common buses. The main processor comprises a bus occupancy signal delay circuit(46) and a transmission port deciding circuit(47). The bus occupancy signal delay circuit(46) delays bus occupancy signals for a predetermined time, to occupy the common bus generated in the controller of an arbitrator. And the transmission port deciding circuit(47) decides the main transmission port according to the control of the CPU of the peripheral processors, and controls a not-delayed bus occupancy signal to be transmitted to the decided transmission port, and a delayed bus occupancy signal to be transmitted to another transmission port.
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