发明名称
摘要 <p>PURPOSE:To simplify the control in the case of broadcasting the same packet to plural outgoing lines by storing the same packet inputted in time division multiplexing to plural idle addresses different from a buffer memory simultaneously. CONSTITUTION:A packet inputted from plural incoming lines 101, 102 is subjected to time division multiplex by a time division multiplexer circuit 103 and the result is inputted to a buffer memory 104. A control circuit 111 extracts idle address information by the number of broadcast stations from a FIFO memory 105 based on each packet inputted in the buffer memory 104 and sends the information to the buffer memory 104, which stores the same packet to different idle addresses. In the case of broadcasting a packet, sets of idle address information extracted from the FIFO memory 105 are stored one by one to FIFO memories 106, 107 corresponding to outgoing lines 109, 110 to be broadcast and the control circuit 111 extracts one by one packet stored in the memory 104 in time division multiplex according to the idle address information sent from the memories 106, 107 and sends the result to a demultiplexer circuit 108.</p>
申请公布号 JP3082313(B2) 申请公布日期 2000.08.28
申请号 JP19910159358 申请日期 1991.07.01
申请人 发明人
分类号 H04Q3/52;H04L12/18;H04L12/70;H04L12/931;H04L12/933;H04Q11/04;(IPC1-7):H04L12/56 主分类号 H04Q3/52
代理机构 代理人
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