发明名称 EXTERNAL CONTROL CLOCK SIGNAL AND MULTIPLEXER
摘要 PROBLEM TO BE SOLVED: To attain transmission of data when no external clock from a modem is given to a buffer in a low speed channel. SOLUTION: Clock input interruption detection circuits 106, 107 connect to an external clock side in a low speed channel to monitor the state of the external clock. If input of S side and R side external clocks ST1, ST2 is interrupted, an S side clock selector 103 and an R side clock selector 104 are controlled to select an internal clock RT in a low speed channel respectively.
申请公布号 JP2000068988(A) 申请公布日期 2000.03.03
申请号 JP19980237721 申请日期 1998.08.24
申请人 NEC ENG LTD 发明人 OZAWA SEIICHI
分类号 H04L1/22;H04J3/04;H04L7/00 主分类号 H04L1/22
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