发明名称 BUS ACCESS CONTROL CIRCUIT
摘要 PROBLEM TO BE SOLVED: To improve the writing/reading performance of a memory and the processing capacity of an MPU and to shorten the occupied time of buses with respect to a bus access control circuit connected to the terminals of an MPU bus, a memory bus, an I/O bus, and so on. SOLUTION: A memory access control circuit 11 receives memory bus using requests from the MPU 1, an I/O 3 and a stand-by memory 9 and provides use permission to these devices so as not to collide with each other. Thereby the MPU 1, the I/O 3 and the memory 9 can orderly acquire the use permission of the memory bus C and share the memory C. A memory access control circuit 10 has a function for converting an MPU bus A, an I/O bus B and a memory bus C into a common protocol.
申请公布号 JP2000029823(A) 申请公布日期 2000.01.28
申请号 JP19980193278 申请日期 1998.07.08
申请人 FUJITSU LTD 发明人 SHINOHARA SHIGERU;NAKAHARA HIDETOSHI;FUJIZONO KENJI;ISHIKAWA YASUHIRO
分类号 G06F13/18;G06F13/36;(IPC1-7):G06F13/36 主分类号 G06F13/18
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