| 摘要 |
<p>Disclosed herein is a non-volatile semiconductor storage device having a plurality of non-volatile memory cells formed by cell transistors (CTr1) in which a first voltage is applied to a word line (WL) through an address selection circuit (11) and a second voltage lower than the first voltage is applied to the transistors (STr1 and STr2) through a selection line (SL) and/or a bit line (BL). The voltage applied to the transistors (CTr1, STr1 and STr2) is lower than that conventionally employed. Accordingly, a withstand voltage of the transistor (CTr1, STr1 and STr2) can be reduced to decrease the occupied area of the transistors (CTr1, STr1 and STr2) and the like to realize higher integration. <IMAGE></p> |
