发明名称 |
Layout structure for barrel shifter with decode circuit |
摘要 |
Two flip-flops and decode circuits are provided. Whereas the one flip-flop receives 1-bit bit-shift-amount data B(1), the other flip-flop receives 1-bit bit-shift-amount data B(0). The decode circuits decode the bit-shift-amount data from the flip-flops. The flip-flops and the decode circuits are laterally laid out in a line. The flip-flops and the decode circuits are symmetrically laid out in bits, together with four flip-flops that receive respective 1-bit data to be bit-shifted (data A(3) to A(0)) and a bit shifter that bit-shifts the data A(3) to A(0) for a bit shift amount from said decode circuits, to form a bit slice structure and to be arranged within a data path. Accordingly, it is possible to achieve an effective reduction of the length of signal wiring over which bit-shift-amount data propagate. The reduction of wire load can be accomplished. The speed-up of data bit shift processing can be realized.
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申请公布号 |
US5941937(A) |
申请公布日期 |
1999.08.24 |
申请号 |
US19970959374 |
申请日期 |
1997.10.28 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
YAMAMOTO, HIROAKI;NISHIMICHI, YOSHITO |
分类号 |
G06F5/01;(IPC1-7):G06F5/01 |
主分类号 |
G06F5/01 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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