Processor microarchitecture for efficient processing of instructions in a program including a conditional program flow control instruction

摘要

A processor microarchitecture for efficient processing of instructions in a program including a program flow control instruction. The program flow control instruction specifies a target instruction and includes one or more candidate instructions between the target instruction and the program flow control instruction. A fetch unit fetches instructions in the program from the memory. Control logic stores one or more candidate instructions in the buffer prior to resolution of the conditional program flow control instruction in response to the fetch unit fetching a program flow control instruction specifying a target instruction within a predetermined number of instructions from the conditional program flow control instruction. In another embodiment, the candidate instructions are stored only if the conditional branch instruction is considered to be difficult to predict. The execution unit of the invention executes the candidate instructions if the conditional program flow control instruction is resolved to be not taken and ignores the candidate instructions, through no-ops in one embodiment, if the conditional program flow control instruction is resolved to be taken, thus avoiding a misprediction penalty.