Sense amplifier and or gate for a high density programmable logic device

摘要

A high density programmable logic device (PLD) having sense amplifiers and OR gates configured to increase operation speed and reduce transistor count from previous circuits as well as to provide a selectable power down mode on a macrocell-by-macrocell basis. The sense amplifiers include a single cascode in the data path connecting a product term to the OR gates. The OR gates utilize a plurality of source follower transistors followed by pass gates to provide logic allocation enabling the sense amplifier outputs to be reduced from the 0.0 V-5.0 V CMOS rails to increase switching speed while reducing overall transistor count. Amplifying inverters normally provided in the sense amplifiers to provide the CMOS rail-to-rail switching and which would require complex feedback for providing power down on a macrocell-by-macrocell basis are moved forward into OR output circuits. Power down on a macrocell-by-macrocell basis is provided by selectively sizing the amplifying inverters in the OR output circuits.