| 摘要 |
A high speed, feed forward, segmented neural network includes a plurality of network layers stacked (12) in an ascending pyramid fashion. The network layers are structured with a plurality of subnetworks, and within each subnetwork exists a plurality of nodes (22, 24, 26) structured in a fully interconnected and/or partially interconnected layered neural network arrangement. The inputs and outputs of each subnetwork are one bit digital values constrained to '0' or '1', while any number of nodes with any number of layers may be modeled for each subnetwork. Each subnetwork is independent of all other subnetworks in a given network layer, and thus, each network layer is segmented. In hardware implementation, each subnetwork comprises a simple memory device, such as a RAM or PROM look-up table. The speed of the neural network system is high and largely dictated by the access time of the memory devices used. A network fabrication approach is also presented. <IMAGE> |
