发明名称 TRANSMISSION LINE WITH VARIABLE CHARACTERISTIC IMPEDANCE
摘要 PURPOSE:To reduce the wiring width of a low impedance transmission line, to decrease the chip size of a high frequency semiconductor integrated circuit and to reduce the development turnaround time (TAT) by forming a conductor film in Schottky junction with a semiinsulating chemical semiconductor substrate onto the substrate. CONSTITUTION:An N<+> injection layer 3A is formed to a semi-insulation GaAs substrate 2A by ion implantation and a 1st dielectric film 4A made of a silicon oxide whose thickness is 1mum is provided. A stripe shaped open hole whose width is 8mum is provided to the film 4A and an Au film of 2mum thick and 10mum wide is coated to form a conductor film 7A in Schottky junction with the N<+> injection layer 3A. Moreover, a silicon nitride film whose thickness is 250nm is laminated as an interlayer insulation film being a 2nd dielectric film 5A and a strip conductor film 6A is provided. Then the Schottky junction is biased reversely. Thus, the trimming of an input output matching circuit is implemented by an external bias and the turnaround time (TAT) is considerably reduced.
申请公布号 JPH03210803(A) 申请公布日期 1991.09.13
申请号 JP19900005110 申请日期 1990.01.12
申请人 NEC CORP 发明人 SAITO YASUO
分类号 H01L21/3205;H01L21/822;H01L23/52;H01L27/04;H01P3/08;H01P5/04;H01P11/00 主分类号 H01L21/3205
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