发明名称 DESIGNING METHOD FOR SEMICONDUCTOR ELEMENT
摘要 PURPOSE:To easily mount a semiconductor element on different packages by a method wherein a figure data of a chip is input to a CAD apparatus, a wiring standard is compared and judged and common positions of pads to be connected on a lead frame and on the semiconductor element are designed. CONSTITUTION:An external-shape data of a semiconductor chip 3 is input to a CAD apparatus. The chip 3 is mounted on a mounting part of a lead frame; temporarily set imaginary electrode pad positions of a pad arrangement line 5 connected to the center of electrode pads of the chip 3 are connected to inner leads 1 corresponding to them. Then, temporarily wired lines are compared with a wiring standard regarding whether they are within a prescribed length or whether an inclination angle to a horizontal line of interconnections is within a prescribed value; it is judged whether they are within a prescribed value. A connectable range 4 which is set by the electrode pads to be connected to the individual leads 1 is decided. Then, positions of the electrode pads, i.e., pad coordinates 6, are set in positions to make the interconnections shortest in a position range common to the lead frame. Thereby, it is possible to obtain an element which can be mounted on different packages.
申请公布号 JPH0357235(A) 申请公布日期 1991.03.12
申请号 JP19890193022 申请日期 1989.07.25
申请人 NEC CORP 发明人 MORI NOBUYUKI
分类号 H01L21/60;G06F17/50 主分类号 H01L21/60
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