发明名称 |
Multiprocessor bus protocol |
摘要 |
A bus protocol system for interprocessor communications in valves polling the processors of a multiprocessor unit in an open loop fashion to determine which processors are ready to send. Upon completion of a simultaneous poll of all processors the system identifies which processor are ready to send by utilizing a send mask generated by the ready processors. The ready processors are sequentially selected as send processors and granted access to the bus for a complete data transfer cycle unless the selected processor indicates it is not ready to send. The system also includes a timing signal system that provides for a high data transfer rate. A send clock signal strobes words onto the bus from a send processor and a receive clock signal loads words from the bus to a receive processor. The send processor generates the receive clock signal by delaying the send clock signal by a fixed delay, DR.
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申请公布号 |
US4888684(A) |
申请公布日期 |
1989.12.19 |
申请号 |
US19860845906 |
申请日期 |
1986.03.28 |
申请人 |
TANDEM COMPUTERS INCORPORATED |
发明人 |
LILJA, DAVID J.;ZACHER, A. RICHARD;WIERENGA, STEVEN W. |
分类号 |
G06F11/20;G06F13/22;G06F13/42 |
主分类号 |
G06F11/20 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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