| 摘要 |
A bus arbitration system for use in a data processing system which operates on clocked cycles for determining priorities in accessing a system memory and one or more local memories associated with processor units is shown. Each of the processor units are operatively coupled through a local bus to its associated local memory. A system bus interconnects the processor units and local memories in parallel to the local bus and the system is connected to an input/output device and the system memory. The bus arbitration system monitors requests made by processor units or the input/output device for access to the system memory or a local memory during the clock cycle. A determination section of a bus arbitration module determines whether access is available over the system data bus or a local data bus. A priority logic section identifies the existence of a conflict due to one or more of the processor units and the input/output device requesting access over the system bus to either the system memory or the same associated local memory during the clock cycle and for granting a request to a selected one of the processor units or the input/output device for accessing either the system memory or one of the associated local memories over the system bus. When a processor unit is denied access to the system bus, and in the absence of a conflict in request for the same associated local memory, a request is granted to a processor unit to access its associated local memory over its local bus during the clock cycle.
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