| 摘要 |
An ALU having improved propagate and generate signal section as well as carry and sum logic section to decrease the propagation delays. The propagate and generate signal section is specifically designed to be used with a dual ported RAM such that transition of the precharged RAM outputs to the desired outputs are used to trigger the logic. Latches, which are an integral part of the output of the propagate and generate signal section and are latched by the high/low transition of the output and reset by precharge signal, are used in combination with a special control sequence of the logic select of the propagate and generate section to isolate the latch and output such that one of the buses though the ALU may be used as a bidirectional bus so that the ALU may write back into the RAM without intermediate registers or latches. To reduce the length of interconnects and number of crossovers when the ALU includes a shifter/swapper for BCD operations, the carry and sum logic units are grouped by nibbles and are interleaved. Also, the carry and sum logic of nibbles other than the first nibble have carry look ahead logic such that only a single delay is experienced per nibble to produce a carry nibble. The delay of the logic sections are reduced by precharging the drain of each of the FETs in the input logic.
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