CONTROL CIRCUIT OF CLOCK SIGNAL

摘要

PURPOSE:To obtain a clock signal controlling circuit provided with a clock signal stoppage delaying function by suppressing a clock stopping operation by the number of preset cycles of a clock signal by a control signal after a clock stop signal is inputted. CONSTITUTION:When a clock signal CLK is inputted into FFs 1a and 1b and a clock stop signal STOP is inputted into the FF1a asynchronously to the CLK signal, H-level signals are inputted into an AND gate from the Q2 output of the FF1b by the prescribed number of cycles of the CLK signal. A control signal inputted next is identified by a decoder 2 and the signal is held by the number of cycles of the CLK signal previously set in FFs 1c and 1d, then, each output of the decoder 2, FF1c, and FF1d is inputted into an NOR gate. When each output of the decoder 2, FF1c, and FF1d is at H level, the output of the NOR gate is at an L level, and the signal STOP from the Q2 output of the FF1b is suppressed. After each input signal of the NOR gate attains to L level, the signal STOP is outputted from an OR gate.