| 摘要 |
PURPOSE:To always produce digital data on the basis of an accurate slicing level by providing a slice level compensating means which works in response to two types of phase difference signals corresponding to the phase difference component between the output data given from a data slicing circuit and the reading clock signal delivered from a phase locked loop circuit. CONSTITUTION:When a slice level exceeds the normal level V1, the phase is varied for the EFM signal delivered from a data slicing circuit 14. The signals are generated at the output terminals Q of D-FF circuits 30 and 32 by the EFM signal. The signals shown in figures (f) and (g) are produced at the output terminals of D-FF circuits 37 and 38 on the basis of the signals shown in figures (d) and (e) and a synchronizing clock signal. Then finally the signals shown in figures (h) and (i) are delivered from output terminals of an OR circuit 42 and an AND circuit 43 respectively. The polarities of these signals are inverted by NOT circuits 44 and 45 and synthesized each other. This synthesized signal corresponds to the variance of the slice level and is supplied to the inverse terminal of a differential circuit 25. Thus the output voltage of an LPF13 is reduced down to a normal slice level. |
