| 摘要 |
<p>A computer having a control unit (CU) provided with at least one microprogram elaboration unit (EU) which is connected with an input/output control unit (IOU) and with an address formation unit (AF) of at least one main memory (MM), wherein said control unit (CU) is connected in parallel with a plurality of execution modules (XMn), each of which comprises a programmable switch matrix (XSM), to which an internal elaboration unit (XEU), an additional unit for the formation of memory addresses (XAF) and at least one programmable gate matrix (XGn) are connected, respectively. <IMAGE></p> |
