| 摘要 |
<p>PURPOSE:To perform high speed operation with a simple circuit constitution, by performing a butterfly operation for a pipeline system in each stage and performing the pipeline type operation as a whole stage. CONSTITUTION:An address line 13 for readout is respectively connected to the 1st and 2nd input/output memories Mi1, Mi2 of stages S1-Sm and a memory Mi0 for rotating factor, and an address line 14 for write is respectively connected to the memories Mi1 and Mi2. At each stage, one of the memories Mi1 and Mi2 is read out and the other is used for write. Each data read out from the memories Mi1, Mi2 and Mi0 at each stage is applied to a corresponding operation unit AUi. The result of operation at each unit AUi is applied to the 1st and 2nd input/output memories of the next stage, written in a memory not used for readout and the result of operation at the final stage is written in one of output buffer memories M01, M02.</p> |
