| 摘要 |
PURPOSE:To adjust a clock to the least error condition by altering a frequency dividing ratio in accordance with an error or the error of precision of respective clocks. CONSTITUTION:An output signal of a reference oscillator 1 is input into a display 5 for time by way of a frequency dividor 2 and a counter 3. Now, as a ''reset to zero'' signal for second plate is so input into a terminal 9 as to be set by a time signal, then a counting value in a place for the second is retained in a retaining circuit 6 and the place for second in the counter 3 is reset. Further, the retained content is operated together with the corrected condition, which is corrected at the time when the former ''rest to zero'' signal for second place generated, through a operating circuit 7. Therefore, a frequency dividing ratio, which is to be corrected with a correcting circuit 11 for the frequency division, is controlled in accordance with the new corrected condition, thereby, the frequency dividing ratio of the frequency dividor 2 is altered. |
