| 摘要 |
PURPOSE:To enable to interprete the reception with a simple circuit for higher speed transmission signal in comparison with the operating speed of CPU, by connecting the shift clock terminal of the sift register inputting the transmission signal from the serial input terminal to the clock pulse producing circuit output terminal via the analog switch. CONSTITUTION:The reception transmission signal is inputted via the third analog switch 9 to the serial input terminal D of the shift register 1, and the serial output terminal 0 is connected to the input terminal i1 of the CPU2. Further, the shift clock terminal CLK is connected to the output terminals 0, 0 of the first and second analog switches 4 and 5, and the control terminals c, c are connected to the ol terminal of CPU2. Further, the input terminal i of the switch 5 is connected to the output terminal o of the clock pulse generating circuit 3. |
